`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date:    18:00:50 03/31/2014 
// Design Name: 
// Module Name:    RAM 
// Project Name: 
// Target Devices: 
// Tool versions: 
// Description: 
//
// Dependencies: 
//
// Revision: 
// Revision 0.01 - File Created
// Additional Comments: 
//
//////////////////////////////////////////////////////////////////////////////////
module RAM(data_out, //input
			  address,data_in,read,write,clk); //output	  

output [7:0] data_out;
input [7:0] data_in;
input [7:0] address;
input read, write, clk;
reg [7:0] RAM[255:0];

assign data_out = (read) ? RAM[address] : 8'd0;

always @ (posedge clk)
	if(write) RAM[address] = data_in;

endmodule
